High-voltage integrated CMOS circuit

ABSTRACT

The invention relates to an integrated CMOS circuit comprising, in a semiconductor substrate ( 1 ) with a first type of conductivity, a casing ( 2 ) of a second type of retrograde-doped conductivity, the end of said casing being covered by an inter-casing insulating region ( 4 ). The components contained in said casing are separated from each other by means of intra-casing insulating regions ( 6,7 ). The first insulating elements ( 15 ) of the second type of high-level doping conductivity extend under each intra-casing insulating region. A second region ( 21 ) of the second type of high-level doping conductivity partially extends under the inter-casing insulator beyond the periphery of each casing.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the manufacturing of a CMOS-typeintegrated circuit.

2. Discussion of the Related Art

In a CMOS-type integrated circuit, various components are formed withinproperly doped wells. The substrate is of a first conductivity type, forexample, an N-type epitaxial layer laid on an N⁺-type wafer, and wellshaving a conductivity type opposite to that of the substrate, forexample P wells, will more specifically be considered herein in the casewhere they have a retrograde doping. A retrograde doping well is a wellformed by a succession of at least one deep implantation at a highdoping level and at least one shallower implantation at a lowerconcentration. Such structures have the advantage of reducing thenecessary thermal processings and limiting the gain of verticalparasitic transistors.

An example of such a structure is illustrated in FIG. 1. A lightly-dopedN-type substrate 1 is formed, for example, of an epitaxial layer formedon a heavily-doped N-type silicon wafer. In this substrate is formed aP-type well 2 with a retrograde doping. The periphery of well 2 isdefined by an insulating area 4 located at the surface of epitaxiallayer 1. This insulating area may be a thick oxide layer resulting fromthe manufacturing method commonly known as the LOCOS method. However,any other method for forming an insulating peripheral layer, forexample, digging and filling up of a trench, may be used. Insulatingarea 4 will here be called the inter-well insulating area.

In well 2, active areas 8, 9, 10 within which semiconductor componentscan be formed are defined by thick oxide regions 6, 7, here calledintra-well insulating areas. In the drawing, an N-channel MOS typetransistor has been shown in each of these regions. As the structure ofthese components is not the object of the present invention, saidcomponents are shown extremely schematically and will not be describedin detail, but those skilled in the art will know how to form suchcomponents in various ways and with various structure alternatives.

Outside of the perimeter defined by inter-well oxide area 4, are presentother elements of a circuit formed in the silicon wafer. These may beother P wells or, as shown, P-channel MOS-type transistors 12 directlyformed in epitaxial layer 1 and delimited by other intra-well insulatingregions such as region 14. These may also be components formed in N-typewells specifically doped to optimize components to be formed therein.

P-type doped areas 15, conventionally called insulation implantations,formed under each of intra-well insulating areas 6, 7, have also beenshown in FIG. 1. Insulation implantations 15 are conventionally formedbefore insulating regions 6, 7 by implantation at a relatively highdoping level, to result in regions having a surface doping level on theorder of from 10¹⁷ to 10¹⁸ atoms/cm³. Insulation implantations 15 aim atavoiding creation of lateral parasitic transistors which would forexample have a source corresponding to the drain of a transistor on oneside of insulating region 7, a drain corresponding to the source of atransistor on the other side of insulating region 7, and a channelcorresponding to the upper portion of the P-type well under theinsulating region. Such a parasitic transistor could be started by avoltage applied to a metallization running over insulating region 7.Providing an insulation implantation 15 having a relatively high dopinglevel avoids turning on such a parasitic transistor.

As indicated previously, within wells 2, the choice of a structure ofretrograde type enables optimizing many operating parameters of thecomponents, especially reducing the action of vertical parasitictransistors.

However, such retrograde-type wells appear in practice to have a smallerbreakdown voltage in reverse biasing, that is, when well P is negativelycharged with respect to substrate 1, than conventional wells in whichthe doping level progressively decreases from the upper surface to thelower area of the well. It is generally considered that this reducedbreakdown voltage results from the shape of the periphery of thejunction in the area designated by reference 17 and schematically shownin FIG. 1. Instead of a junction having the regular shape designatedwith reference 18 corresponding to a conventional well, the case of aretrograde doping provides a shape in which the periphery of the P wellprotrudes in a hump 19 below the surface of the semiconductor wafer.This hump directly results from the way in which a retrogradeimplantation is performed. Indeed, given that a heavily-doped deepimplantation has first been performed before a shallower morelightly-doped implantation, the deep portion in which the implantationhas been performed with a higher doping level will have the greatestlateral extent. It can be understood that given this shape of thejunction periphery, in reverse biasing, the field lines will tend tocurve back and tighten up, which results in a reduction in the breakdownvoltage.

Various solutions are known to improve this breakdown voltage. A firstsolution consists of forming above insulating area 4 a field plate, thatis, a conductive area connected to the voltage of the well which takespart in the spreading of the field lines when the device isreverse-biased. This solution has a limited efficiency and does not, byitself sufficiently increase the breakdown voltage. It is generallyadopted as a complement to other solutions.

Another solution consists of forming at the periphery of well 2, underinsulating layer 4, a more lightly-doped ring, deeper than the well.This solution is efficient but requires implementing additionaltechnological steps. It can thus not be adopted when the manufacturingcost of a component is desired to be lowered.

SUMMARY OF THE INVENTION

Thus, an object of the present invention is to provide a novelretrograde well periphery structure that improves the reverse breakdownvoltage of this well. The present invention aims at achieving thisobject without increasing the manufacturing cost of a component andwithout increasing the number of technological steps necessary to itsimplementation.

To achieve this and other objects, the present invention provides aCMOS-type integrated circuit including, in a semiconductor substrate ofa first conductivity type, a well of the second conductivity type with aretrograde doping, the limit of said well being covered with aninter-well insulating area, the components contained in said well beingseparated from one another by intra-well insulating areas, firstinsulation regions with a high doping level of the second conductivitytype extending under each intra-well insulating area. A second regionwith a high doping level of the second conductivity type, identical tothe first regions, partially extends under the inter-well insulatorbeyond the periphery of each well.

According to an embodiment of the present invention, the amount by whichthe second region laterally protrudes from the well is of the same orderof magnitude as the well depth.

According to an embodiment of the present invention, the substrate is alightly-doped epitaxial layer formed on a more heavily-dopedsingle-crystal silicon wafer of the first conductivity type.

According to an embodiment of the present invention, the maximum dopinglevel in the depth of the retrograde well is on the order of from 10¹⁷to 10¹⁸ atoms/cm³ and the surface doping level of the second region isof the same order of magnitude.

The foregoing objects, features and advantages of the present invention,will be discussed in detail in the following non-limiting description ofspecific embodiments in connection with the accompanying drawings,wherein:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a conventional CMOS-type structure with a retrograde well;

FIG. 2 shows a CMOS-type structure with a retrograde well according tothe present invention;

FIG. 3 shows the limiting area between two P wells in the structureaccording to the present invention;

FIG. 4 shows the shape of the breakdown voltage between two P wells andbetween a well and the substrate according to prior art;

FIG. 5 shows the shape of the breakdown voltage between two P wells andbetween a well and the substrate according to the present invention.

DETAILED DESCRIPTION

Having thus described at least one illustrative embodiment of theinvention, various alterations, modifications, and improvements willreadily occur to those skilled in the art. Such alterations,modifications, and improvements are intended to be within and scope ofthe invention. Accordingly, the foregoing description is by way ofexample only and is not as limiting. The invention is limited only asdefined in the following claims and the equivalents thereto.

FIG. 2 shows same elements as in FIG. 1 having the same referencecharacters. These elements will not be described again. The differencebetween the structures according to the present invention shown in FIG.2 and the prior art structure shown in FIG. 1 is the structure of thearea peripheral to the well. As previously, this periphery extends undera thick oxide inter-well area 4. Well 2 is a retrograde well formed inthe same way as described in relation with FIG. 1. However, under aportion of insulating inter-well 4, a P-type region 21 has beenimplanted. Region 21 is formed at the same time as insulationimplantations 15 formed under insulating intra-well areas 6 and 7.Region 21 is formed to protrude from the well periphery by a chosenamount. In practice, a protrusion on the order of from 2.5 to 5 μm, thatis, of the same order of magnitude as the well depth, appears, with theorders of magnitude which will be given hereafter, to be sufficient toachieve the breakdown voltages of the same order of magnitude as thevoltages which would be achieved with conventionally-formed wells, thatis, wells having a doping level which regularly decreases from thesurface to the inside of a semiconductor wafer.

As an example, a CMOS-type structure in which the channel lengths aremuch smaller than 1 μm, for example, 0.35 μm, is considered. It is thenconsidered that well P has a depth smaller than 3 μm, with a doping peakresulting from a deep implantation located at a depth slightly smallerthan 2 μm and with a maximum doping concentration on the order of from10¹⁷ to 10¹⁸ atoms/cm³. With a conventional retrograde structure such asillustrated in FIG. 1, the reverse breakdown voltage would be on theorder of 60 volts. With a structure according to the present invention,a breakdown voltage on the order of 77 volts is obtained if extension 21according to the present invention protrudes by approximately 3 μm withrespect to the normal well periphery and a voltage greater than 80 voltsis obtained as soon as this value exceeds 5 μm. Of course, the structureaccording to the present invention may also be associated with fieldplates, as previously mentioned.

The case of the breakdown voltage in an area included between two Pwells will now more specifically be considered. Such a structure isschematically shown in FIG. 3. A first retrograde P well 31 is formed tothe left of the drawing and includes a junction extension 32 formed of aheavily-doped shallow P-type insulation implantation. To the right ofthe drawing appears a second P well of retrograde type 33 also providedwith a relatively heavily-doped P-type peripheral extension 34. Thelimits of the two wells extend from an insulating inter-well layer,currently made of thick oxide, 36.

FIG. 4 illustrates breakdown voltages BV according to the distance dbetween the two wells 31 and 33, when regions 32 and 34 according to thepresent invention are not provided. Curve 41 shows the reverse biasingbreakdown voltage between a well and the substrate (epitaxial layer 1)and curve 42 shows the breakdown voltage between two wells biased inopposite ways. The ordinates (BV) represent the breakdown voltage involts and the abscissas represent distance d between two wells in μm.Curve 41 shows that the well-substrate breakdown voltage decreases asthe distance between wells increases. Conversely, curve 42 shows thatthe breakdown voltage between wells increases as the distance betweenthe wells increases. In the example shown, and for the chosen dopinglevels, it can be seen that the optimal compromise corresponds to adistance between wells on the order of 6 μm and that the breakdownvoltage then ranges between 60 and 65 volts.

In FIG. 5, curves 43 and 44 respectively correspond to curves 41 and 42in the case where well extension regions 32 and 34 such as illustratedin FIG. 3 have been provided. The conditions are the same as those ofFIG. 4. The well extensions have an extent on the order of 3 μm. Thecurves have the same general shape as those of FIG. 4, but it should benoted that the breakdown voltage for the ideal compromise is now between70 and 75 volts. The optimal distance is on the order of 13 μm betweenthe wells, that is, approximately 7 μm between the ends of the junctionextensions according to the present invention.

It should further be noted that the structure according to the presentinvention has an additional advantage to be added to the fact that thebreakdown voltage is increased: in the vicinity of the optimal area, thebreakdown voltages, be it for the well-well breakdown voltage or for thewell-substrate breakdown voltage, vary much more smoothly, that is, thesetting is much less critical.

Thus, the present invention enables increasing the well-substrate andwell-well breakdown voltage in a CMOS integrated circuit structure witha retrograde well and this can be performed without complicating themanufacturing process since the only modification is a modification ofthe mask of the insulation implantations. While, in prior art, theseimplantations would only exist under the intra-well insulating areas, itis additionally provided according to the present invention to formthese doped areas also at the periphery of the P wells, under theinter-well insulating area.

Of course, the present invention is likely to have various alterations,modifications, and improvements which will readily occur to thoseskilled in the art. Although it has been specifically described in thecase of P wells, it can also apply in the case where all conductivitytypes are inverted, that is, in the case of an N well formed in a P-typeepitaxial layer.

Having thus described at least one illustrative embodiment of theinvention, various alterations, modifications, and improvements willreadily occur to those skilled in the art. Such alterations,modifications, and improvements are intended to be within and scope ofthe invention. Accordingly, the foregoing description is be way ofexample only and is not as limiting. The invention is limited only asdefined in the following claims and the equivalents thereto.

1. A CMOS-type integrated circuit including, in a semiconductorsubstrate of a first conductivity type, a well of the secondconductivity type with a retrograde doping, a limit of said well beingcovered with an inter-well insulating area, the well having componentscontained therein, the components being separated from one another byintra-well insulating areas, the integrated circuit further includingfirst insulation regions with a high doping level of the secondconductivity type extending under each intra-well insulating area,wherein a second region with a high doping level of the secondconductivity type, identical to the first regions, partially extendsunder the inter-well insulating area beyond a periphery of the wellwithout reaching a neighboring well.
 2. The CMOS integrated circuit ofclaim 1, wherein an amount by which the second region laterallyprotrudes from the well is of the same order of magnitude as a depth ofthe well.
 3. The CMOS integrated circuit of claim 1, wherein thesubstrate is a lightly-doped epitaxial layer formed on a moreheavily-doped single-crystal silicon wafer of the first conductivitytype.
 4. The CMOS integrated circuit of claim 1, wherein a maximumdoping level in the depth of the retrograde well is on the order of from10¹⁷ to 10¹⁸ atoms/cm³ and a surface doping level of the second regionis of the same order of magnitude.
 5. A CMOS-type integrated circuit,comprising: a substrate of a first conductivity type; at least one well,disposed in the substrate, of a second conductivity type, the at leastone well having a retrograde doping and a periphery, a plurality ofcomponents disposed in the at least one well; at least one intra-wellinsulating area disposed between adjacent ones of the plurality ofcomponents in the at least one well; at least one first insulationregion extending under each intra-well insulating area, the at least onefirst insulation region having a first high doping level of the secondconductivity type; an inter-well insulating area that covers at least aportion of the periphery of the at least one well; and a second regionthat partially extends under the inter-well insulating area beyond theperiphery of the at least one well, the second region having a secondhigh doping level of the second conductivity type; wherein the at leastone well comprises a plurality of wells; wherein the plurality of wellscomprises at least first and second neighboring wells, and wherein thesecond region of the first well does not extend to the second well. 6.The CMOS-type integrated circuit of claim 5, wherein the first highdoping level equals the second high doping level.
 7. The CMOS-typeintegrated circuit of claim 5, wherein the well has a depth, and whereinan amount by which the second region laterally extends beyond theperiphery of the well is of the same order of magnitude as the welldepth.
 8. The CMOS-type integrated circuit of claim 5, wherein thesubstrate is a lightly-doped epitaxial layer formed on a moreheavily-doped single-crystal silicon wafer of the first conductivitytype.
 9. The CMOS-type integrated circuit of claim 5, wherein a maximumdoping level in a depth of the retrograde well is on the order of 10¹⁷to 10¹⁸ atoms/cm³ and a surface doping level of the second region is ofa same order of magnitude as the maximum doping level.